This invention is directed to high density metal-oxide-semiconductor devices, and more particularly, to a high density metal-oxide-semiconductor field effect transistor structure having thicker oxide at the gate edges and metal silicide regions in the source, drain and gate.
Since the invention of the integrated circuit there has been a constant effort directed toward increasing the number of components per unit of chip area. This has been done both by improvements in existing technologies and by the invention of new technologies. The first integrated circuits were bipolar in operation and used junction isolation to achieve electrical isolation of individual components. However, the self-isolating metal-oxide-semiconductor devices with their inherently higher packing density have substantially replaced bipolar devices in microprocessors and memories, areas where very high packing density is required. As the demand for faster, higher density metal-oxide-semiconductor devices continues, improvements in fabrication technology are necessary to keep pace with the demand. Today efforts are being made toward increasing device density and speed by decreasing component geometries, junction depths, oxide thicknesses, etc., device speed usually improving as the packing density increases Oxide thickness must be scaled down along with reductions in other parameters but oxide breakdown problems such as interconnect to interconnect breakdown in multilevel interconnect systems arise as the oxides get thinner. Component geometries must obviously decrease if packing density improvements are to be achieved. Junctions depths must be reduced to avoid punch-through from source to drain, and gate overlap of source and drain must be reduced to minimize gate-to-source and gate-to-drain capacitances which reduce device speed. Recent work in that area is shown in copending applications, "METHOD OF FABRICATING SILICON GATE FIELD EFFECT TRANSISTORS IN A MULTILEVEL INTERCONNECT SYSTEM AND STRUCTURE RESULTING THEREFROM," by Al F. Tasch, Jr. and Horng-Sen Fu, Ser. No. 72,803 filed Sept. 5, 1979 and "METAL-OXIDE-SEMICONDUCTOR DEVICES USING METAL SILICIDE REGIONS TO IMPROVE DEVICE SPEED AND PACKING DENSITY", by Al F. Tasch, Jr. and Pallab K. Chatterjee, Ser. No. 92,009, filed 11-7-79. However, as junction depths and component geometries are reduced, the resistance and/or sheet resistance of the resulting component elements (e.g. sources, drains, gate electrodes, etc.) will increase. This becomes a major problem with existing and future designs since long, thin, narrow interconnect strips (e.g. gate electrodes) and long, narrow, shallow doped regions (e.g. sources and drains) are necessary to achieve high density device layouts. As the resistance of the doped regions increases to a certain point, these regions cannot be used for interconnects. This will have a negative impact on device size. Also, the high series resistance of the sources and drains will degrade device performance especially at lower power supply voltages. As the resistance of the polycrystalline gate electrodes increases the RC time constant associated with the electrode will increase and slow down device speed.